Example 12: ULPS Operation at D-PHY RX (Slave) Clock Lane - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The RX clock lane ULPS entry is indicated by assertion of rxulpsclknot (active-Low) along with assertion of ulpsactivenot (active-Low) signal. ULPS exit is marked by reception of MARK-1 on the line and ulpsactivenot is deasserted. After receiving MARK-1 for T_WAKEUP time (1 ms minimum), rxulpsclknot is deasserted. This behavior is shown in the following figure.
Figure 1. D-PHY RX (Slave) ULPS Mode Operation for Clock Lane