Core Configuration Tab - 4.3 English - PG202

Component Name

Core Parameters

D-PHY Lanes

Select the number of data lanes to be used in the core. The valid range for TX is from 1 to 4, and for RX is from 1 to 8.

Line Rate

Enter a line rate value in megabits per second (Mb/s) within the valid range: 80 to 3200 Mb/s based on the device selected. The Vivado IDE automatically limits the line rates based on the device selected. For details about family/device specific line rate support, refer to the respective device data sheet. For example:

Table 1. MIPI D-PHY Performance Zynq UltraScale+ MPSoC

Description	I/O Bank Type	Conditions 1	Speed Grade and VCCINT Operating Voltages					Units
			0.90V	0.85V		0.72V
			-3	-2	-1	-2	-1
Maximum MIPI D-PHY transmitter or receiver data rate per lane.	HP	XC and XA devices usingVivado tools 2019.2.2 or later.	2500	2500	2500 2	2500	1260	Mb/s
		XC and XA devices usingVivado tools 2019.1.1 through 2019.2.1.	2500	2500	1260	2500	1260	Mb/s
		XC and XA devices usingVivado tools 2019.1 or earlier.	1500	1500	1260	1260	1260	Mb/s
		XQ devices	1500	1500	1260	1260	1260	Mb/s
		All devices in SBVA484, SFRA484, UBVA494, and UBVA530 packages.	1260	1260	1260	1260	1260	Mb/s
For applicable conditions, the lower maximum data rate applies. XA devices with the -1Q speed grade require Vivado tools 2020.1, or later, for data rates greater than 1260 Mb/s. Refer to Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) for latest updates.

Data Flow

Select the options for the direction of the data transfer. Available options are TX (for Master) and RX (for Slave).

Enable Splitter Bridge Mode

Select this to enable splitter bridge mode. This allows replication of the received MIPI camera stream to multiple (1 to 4) MIPI output streams for further processing by external modules.

Number of TX Interfaces

Select the number MIPI output TX interfaces when Enable Splitter Bridge Mode is selected. You can select up to four TX interfaces. Based on number of TX interfaces selected, the GUI allows I/O configuration for all these interfaces separately. I/Os of each TX interface can be in the same bank or a different bank.

Note: Ensure all TX I/Os are exclusive and follow IO guidelines.

Escape Clk (MHz)

Enter a valid escape clock frequency in MHz into the text box for the MIPI D-PHY Master (TX) core. The valid range is from 10.000 to 20.000 MHz. Applicable only for the MIPI D-PHY TX core.

LPX Period (ns)

Enter a valid LPX Period in nanoseconds (ns) into the text box for MIPI D-PHY Master (TX) core. The valid range is from 50 to 100 ns.

D-PHY RX ULPS WAKEUP counter for 1 ms time

Select the option to include 1 ms WAKEUP counter. Otherwise, D-PHY RX IP checks only for the LP-10 transition to exit from the ULPS mode.

Note: Available only for D-PHY RX configurations.

Resource Optimization presets

By using the mentioned presets, you can reduce the resources depending upon the requirements.

If preset CSI2RX_XLNX is selected, the ULPS and LPDT features are not supported by the core.

If preset CSI2RX_XLNX2 is selected, the ULPS and LPDT features, errorsotsynchs assertion, and the checking of the LPX period are not supported by the core.

If preset CSI2TX_XLNX is selected, the ULPS and ESC features are not supported by the core; furthermore, the register interface is removed, and the clock and data lane status information is provided through ports.

IODELAY_GROUP Name

This parameter is used to select the IODELAY_GROUP name for the IDELAYCTRL. All core instances in the same bank sharing IDELAYCTRL should have the same name for this parameter. Select a unique name per bank.

Note: Available only for 7 series D-PHY RX configurations.

Enable deskew sequence detection logic

This parameter is used to enable the deskew detection logic. When a deskew packet is received, D-PHY does the eye centering between clock and data.

Note: The minimum required length of the periodic calibration pattern is 2¹³ UI.

Note: When this feature is selected, then the maximum supported lanes is 4.

Enable the SSC Clock

This parameter is used when the SSC feature is required. When this parameter is selected, you must drive the SSC-enabled byte clock (ssc_byteclkhs_in) to the core when the line rate is greater than 2500 Mb/s and when the shared logic is inside the core.

Transmit First Deskew Calibration Sequence

This parameter is used to enable the initial deskew pattern in D-PHY TX configuration.

T_SKEWCAL Parameter for first deskew seq (txbyteclkhs clocks)

This parameter defines the length of the initial calibration sequence.

Transmit Periodic deskew calibration sequence

This parameter is used to enable the periodic deskew pattern in D-PHY TX configuration.

Note: The length of the periodic pattern depends on the length of dl<n>_txskewcalhs.

Line rate supported by device Data sheet

This option is available only for 7 series devices. Select this option if the line rate is within the range of the selected device. Else, refer to the data sheet for line rate limitations.

Guarantees the clock Rising Edge Alignment to first payload bit on serial lines

This option is available for AMD Versal™ adaptive SoC TX configuration. When selected, the first payload bit is aligned to rising edge of the serial clock.

When the option 'Guarantees the clock Rising Edge Alignment to first payload bit on serial lines' is enabled, the first payload bit is aligned to the rising edge if the parameter is disabled. Then the first payload bit cannot be guaranteed to be on the rising edge of the clock.

Figure 3. Option Enabled: Guarantees the lock Rising Edge Alignment to first payload bit on serial lines

Control and Debug

Infer OBUFTDS for 7 series HS outputs

Select this option to infer OBUFTDS for HS outputs.

Note: This option is available only for 7 series D-PHY TX configurations. It is recommended to use this option for D-PHY compatible solution based on resistive circuit. For details, see D-PHY Solutions (XAPP894).

Enable Active Lane support

Select this option to control TX data lanes. Active lanes allows the D-PHY TX to run with lower lanes than IP is configured for. This helps the lane down scaling and disabling any TX data lane by the deasserting corresponding bit in the active_lanes_in bus input. It is recommended to update the active_lanes_in when all data lanes are in stopstate. HS_TX_TIMEOUT is disabled internally when the active_lanes_in feature is exercised. Lane 0 is always enabled (otherwise, txreadyhs is not asserted).

Enable AXI4-Lite Register I/F

Select the AXI4-Lite-based register interface for control and debug purposes.

Protocol Watchdog Timers

Enable HS and ESC Timeout Counters/Registers

Enable the HS_TX_TIMEOUT/HS_RX_TIMEOUT and ESC_TIMEOUT counters. Select this option to enable the HS_TIMEOUT and ESC_TIMEOUT registers provided that the AXI4-Lite register interface is enabled.

HS Timeout (Bytes)

Enter the maximum transmission or reception length in bytes for High-Speed mode. The valid range is from 1,000 to 65,541 bytes.

Escape Timeout (ns)

Enter the maximum transmission or reception length in ns for LPDT escape mode. The valid range is from 800 to 25,600 ns.

Calibration Mode

Select the calibration for 7 series D-PHY RX IP. Available options:

• None (default selection) - Does not add IDELAYE2 primitive.
• Fixed - Sets the IDELAYE2 TAP value given in the IDELAY Tap Value.
• Auto - Adds the IDELAYE2 primitive. IDELAY Tap Value will be configured by D-PHY RX IP based on received traffic and calibration algorithm. IP uses the DIFF_TERM=TRUE setting for input buffers when Calibration mode is set to Auto. Auto algorithm performs a skew calibration on the runtime. It usually requires HS packet reception by D-PHY RX IP to determine the correct IDELAY tap value. This mode is available for line rates above 450 Mb/s.

External IDELAY tap loading

Allows to load IDELAY tap values through external ports in "Fixed" mode of Calibration.

Note: It is recommended to clock these ports through core_clk.

IDELAY Tap Value

Enter IDELAY TAP value used calibration in fixed mode. The valid range is from 1 (default option) to 31.

Include IDELAYCTRL in core

For multiple D-PHY RX IP cores that are sharing single IO bank, select this option to include IDELAYCTRL in the IP for the auto calibration mode. Only one IDELAYCTRL is available per I/O bank. In case of multiple D-PHY RX cores in single I/O bank, only one D-PHY RX IP core should have this option selected. For the rest of D-PHY RX cores, this option should be unselected.

Note: This option is applicable only for 7 series D-PHY RX IP configurations.

Enable 300 MHz clock for IDELAYCTRL

Select this option to connect 300 MHz to IDELAYCTRL and is used in auto calibration mode.

Note:

• This option is applicable only for 7 series D-PHY RX IP configuration.
• For 7 series in AUTO Mode, when there are multiple instances of DPHY and they share the IDELAY control ready from one DPHY instance to other DPHY instance. The DPHY instance which shares the IDELAY controller ready cannot have the Enable 300 MHz clock for IDELAYCTRL parameter set to true.
• For 7 series, internal IP timing is tested and validated to a maximum of 1250 Mb/s. Meeting timing at Line Rates Higher than 1250 Mb/s might be possible depending on setup and are available in the GUI.
  Note: Internal timing limitations are different than physical timing limitations, which are based on the PCB configuration and might be lower. The variables are the use of an external PHY, resistor network and termination options. Validate that the full system can handle the line rate requirement of your design. See D-PHY Solutions (XAPP894) for more information.