Example 10: Low-Power Data Receive with Synchronization Error at D-PHY RX (Slave) Side - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The MIPI D-PHY RX core reports an error to the PPI if the number of received valid bits during LPDT is not a multiple of eight. This is indicated by asserting errsyncesc along with stopstate and remains asserted until the next change in the serial line state. This behavior is shown in the following figure.
Figure 1. Low-Power Data Reception with Synchronization Error at the D-PHY RX (Slave)