The MIPI D-PHY RX core reports an error to the PPI if the number of received
valid bits during LPDT is not a multiple of eight. This is indicated by asserting errsyncesc
along with stopstate
and
remains asserted until the next change in the serial line state. This behavior is shown in the
following figure.
Figure 1. Low-Power Data Reception with Synchronization Error at the D-PHY RX
(Slave)