Pin Assignment Tab - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The following figure shows the I/O pin parameters for the core. For more information on the optimal IO pin assignment, see Appendix C, Pin and Bank Rules.
Note: This tab is not available for 7 series and Versal D-PHY RX configuration.
Figure 1. Pin Assignment Tab
HP IO Bank Selection
Select the HP I/O bank for clock lane and data lane implementation.
Note: This option is not available for 7 series FPGAs as D-PHY can be implemented in both HR bank IO and HP bank IO.
Clock Lane
Select the LOC for clock lane. This selection determines the I/O byte group within the selected HP I/O bank.
Data Lane 0/1/2/3
This displays the Data lane 0, 1, 2, and 3 LOC based on the clock lane selection.