Pin Rules for Zynq UltraScale+ MPSoC Devices - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
This section describes the pin rules for AMD Zynq™ UltraScale+™ MPSoC devices.
  • Clock lane pins are represented with clk_<> and data lane pins are represented with data_<>.
  • D-PHY Interface are numbered from if0 to if7.
  • Byte lanes in a bank are designed by T0, T1, T2, or T3. Nibbles within a byte lane are distinguished by a "U" or "L" designator added to the byte lane designator (T0, T1, T2, or T3). Thus, they are T0L, T0U, T1L, T1U, T2L, T2U, T3L, and T3U.
  • Pins in a byte lane are numbered from 0 to 12.
    Note: There are two PLLs per bank and a D-PHY uses one PLL in every bank that is being used by the interface.