The active-High reset signal core_rst
is used in the
MIPI D-PHY Controller.
The following figure shows the power-on reset behavior for the MIPI D-PHY Controller.
- The
core_rst
signal is asserted for fortycore_clk
cycles. Forty clock cycles are required to propagate the reset throughout the system. - The
mmcm_lock
andpll_lock
signals go Low due tocore_rst
assertion. - The
mmcm_lock
signal is asserted within 100 μs aftercore_rst
deassertion and generates the input clock for the PLL. - The
pll_lock
signal is asserted within 100 μs aftermmcm_lock
assertion. - LP-11 is driven on the lines for T_INIT or longer. This helps the MIPI D-PHY core
complete the lane initialization. Lane initialization is indicated by the
init_done
internal status signal in the waveform. - After LPX_PERIOD of LP-11 assertion,
stopstate
is asserted.
Figure 1. Power on Reset Sequence for the MIPI D-PHY Core
The following table summarizes all resets available to the MIPI D-PHY Controller and the components affected by them.
Functional Block | core_rst | DPHY_EN (Core Enable from Register) | SRST (Soft Reset from Register) | s_axi_aresetn |
---|---|---|---|---|
TX/RX PCS | Yes | Yes | Yes | No |
TX/RX PHY | Yes | Yes | No | No |
Registers | Yes | Yes | Yes | Yes |
Lane Initialization | Yes | Yes | No | No |
The following figure shows the MIPI D-PHY TX IP and MIPI RX IP connected in a system. Config
1 and Config 2 can be in the same or multiple device(s)/board(s).
Figure 2. MIPI D-PHY TX and RX System
The following figure shows the reset assertion sequence for MIPI D PHY Core:
Figure 3. Reset Assertion Sequence for MIPI D-PHY Core