Overview - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English
The top module instantiates all components of the core and example design that are needed to implement the design in hardware, as shown in the following figure. This includes the FRM_GEN, DPHY TX IP, FRM_CHK, and the DPHY RX IP modules.
Figure 1. MIPI D-PHY Core Example Design
The FRM_GEN module generates user traffic for High-Speed mode and low-power data transmission (LPDT). This module contains a pseudo-random number generator using a linear feedback shift register (LFSR) with a specific initial value to generate a predictable sequence of data.
The FRM_CHK module verifies the integrity of the RX data. This module uses the same LFSR and initial value as the FRM_GEN module to generate the expected RX data. The received user data is compared with the locally-generated data and an error is reported if data comparison fails. The example design can be used to quickly get an MIPI D-PHY Controller design up and running on a board, or perform a quick simulation of the module. When using the example design on a board, be sure to edit the <component name>_exdes.xdc file to supply the correct pins and clock constraints.
Important: This implementation is used only for reference and as a demonstration of the example test bench.

Implementing the AMD Versalâ„¢ Example Design:

  1. Once the Example design is open, synthesize the ex-design
  2. Once synthesis is done, open the synthesized design & execute the following command in Tcl console 'xphy::generate_constraints'.
  3. Save the xdc & implement the design.