Pin and Bank Rules for Versal Adaptive SoCs - 4.3 English - PG202

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2024-12-04
Version
4.3 English

This section describes the pin rules for AMD Versalâ„¢ adaptive SoCs.

  • Select any XPIO Bank.
  • RX clock lane pins must be "XCC", "GC/XCC" pins.
  • Non-continuous IO usage is allowed for D-PHY TX and RX interfaces but not recommended.
  • While Selecting the data lane pins for RX it should follow the inter-nibble and inter-byte clocking rules.
Note: Refer to I/O Planning for Versal Devices for detailed pin rules for TX and RX.