Pin and Bank Rules for Versal Adaptive SoCs - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

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4.3 English

This section describes the pin rules for AMD Versalâ„¢ Adaptive SoCs.

  • Select any XPIO Bank.
  • RX clock lane pins must be "XCC", "GC/XCC" pins.
  • Non-continuous IO usage is allowed for D-PHY TX and RX interfaces but not recommended.
  • While Selecting the data lane pins for RX it should follow the inter Nibble & inter byte clocking.
Note: Refer to I/O Planning for Versal Devices for detailed pin rules for TX and RX.