General Checks - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
Release Date
4.3 English
  • Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
  • Ensure that MMCM and PLL have obtained lock by monitoring mmcm_lock_out and pll_lock_out ports respectively.
  • Verify the IO pin planning and XDC constraints.
  • Follow recommended reset sequence.
  • Verify all clocks are connected and are with expected frequencies.
  • Enable AXI4-Lite based register interface to get core status and control.
  • Make sure serial line trace lengths are equal. For PCB Guidelines refer UltraScale Architecture PCB Design User Guide (UG583).
  • Verify the FMC_VADJ voltage to 1.2V in case of FMC card usage.