Register Space - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
Release Date
4.3 English

The MIPI D-PHY core register space is shown in the following table. This register interface is optional and allows you to access the general interconnect states. It also provides control to program protocol timing parameters, such as INIT, and the protocol watchdog timers.

Important: This memory space must be aligned to an AXI 32-bit word boundary.