Revision History - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
Release Date
4.3 English

The following table shows the revision history for this document.

Section Revision Summary
05/10/2023 Version 4.3
Core Configuration Tab Clarified information on 'Guarantees the clock Rising Edge Alignment to first payload bit on serial lines.'
I/O Planning for Versal Devices Updated IP Parameters.
Pin and Bank Rules Added notes for clarification.
04/20/2022 Version 4.3
MIPI D-PHY RX (Slave) Core Architecture Update the images in the section.
Ultra-Low Power State Update this section in Protocol Description.
Core Configuration Tab Added the Table 1 table in the section.
06/30/2021 Version 4.3
I/O Planning for Versal Devices Updated image.
Features Updated the section.
12/11/2020 Version 4.3
General Updates Added information regarding D-PHY support of Versal ACAP.
09/07/2020 Version 4.2
Pin and Bank Rules Hot fix to reinstate section.
07/16/2020 Version 4.2
Core Configuration Tab Added details of new/updated parameters.
Clocking Added clarifications about MMCM and line rate.
PPI Signals Added new signals.
Clocking and Reset Signals Added new signals.
10/30/2019 Version 4.2
General Updates For 7 series fixed mode IDELAY control ready has been incorporated for core operation.
General Updates Added Versal support.
07/02/2019 Version 4.1
General Updates Added 2.5 Gb/s support to the subsystem.
12/10/2018 Version 4.1
General Updates
  • Extended the RX lane configuration from 4 to 8 lanes.
  • Extended the RX register space from 4 to 8 lanes.
  • Figure in Pin Assignment Tab section has been updated.
  • Figure in D-PHY RX Pin Rules section has been updated.
04/04/2018 Version 4.1
General Updates
  • Added Spartan 7 series support
  • Added C_IDLY_GROUP_NAME parameter details
  • Figures in Design Flow Steps chapter have been updated
  • Added a figure in D-PHY RX Pin Rules section
  • Added new IDELAY_TAP_VALUE register details
  • Updated Pin and Bank Rules in Appendix C
10/04/2017 Version 4.0
Minor Updates Minor Updates
04/05/2017 Version 3.1
General Updates
  • Updated system_rst_in port details
  • Updated 7 series calibration ports
  • Removed calibration register (CAL_REG)
  • Added new HS_SETTLE register details
  • Added a new D-PHY RX IP clocking diagram for AMD Zynq™ AMD UltraScale+™ due to constant clkoutphy and MMCM removal
  • Added Pin and Bank Rules
10/05/2016 Version 3.0
General Updates
  • Added 7 series support
  • Updated Figure 3-12 waveform
  • Added Active Lane Support in Chapter 4
04/06/2016 Version 2.0
General Updates
  • Updated D-PHY RX latency numbers
  • Added PKT_CNT field and updated HS_TIMEOUT/ESC_TIMEOUT registers
  • Added Shared Logic feature
  • Updated I/O planning feature
  • Updated Clocking section
  • Added recommended reset sequence for D-PHY in a system
  • Updated the rxvalidhs signal behavior in Example 6 of High-Speed Receive
  • Added Hardware Validation in Appendix
11/18/2015 Version 1.0
Initial Xilinx release NA