Verifying the C/RTL Code - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

When the Export Type specified on the Vitis Model Composer Hub is IP Catalog, Model Composer uses C/RTL co-simulation to verify the RTL output. Again, the objective is to verify that the results of the RTL simulation match the results of the Simulink simulation. In this case, the verification flow is as follows:

  • The Model Composer model is simulated in Simulink to capture the test vectors in signals.stim.
  • Model Composer generates the C/C++ code and the C test bench, tb.cpp.
  • Model Composer runs the C-synthesis and generates the RTL output.
  • Model Composer runs the C/RTL co-simulation. This step ensures the following:
    • That the C++ code generated by Model Composer is correct by comparing with the Simulink simulation, signals.stim.
    • That the RTL code generated by Model Composer is correct by comparing the output stimulus from RTL with C/C++ output.
      Tip: After verification, Model Composer packages the IP for use in Vivado.
  • The result is a separate Pass/Fail returned by Model Composer for both the C-simulation and the C/RTL co-simulation. If the C-simulation fails, the process stops before the C/RTL simulation is run.