The IP Catalog Flow - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

In a Vitis Model Composer design, double-click the Vitis Model Composer Hub block.

As shown in the following figure, you can select IP Catalog compilation by selecting it from the Export Type menu on the Export tab.

Figure 1. IP Catalog

The IP Catalog compilation can be performed for any of the boards or parts your Vivado tools support. In addition to accessing the AMD development boards installed as part of your Vivado installation, you can also specify Partner boards or custom boards (see Specifying Board Support in Model Composer).

The Export Directory field allows you to specify the location of the generated files.

The ... to the right of the Compilation Type field allows you to enter information about the module that will appear in the Vivado IP catalog.

Figure 2. IP Catalog Settings

The Use common repository directory field allows you to specify a directory referred to as the Common Repository. In an IP catalog compilation, the IP created is copied over to this location. If a Vivado user adds this Path as User Repository in the Vivado project's IP Settings, then all IPs that a Model Composer user has placed in this Common Repository will automatically be picked up by Vivado and can be used either in an IP integrator or an RTL flow.

The Use Plug-in project field is used to specify a Vivado project containing an IP integrator Block Diagram (BD) that has been imported into Model Composer.

When you click the Export button, the IP catalog generation flow starts. Navigate to the specified HDL subsystem source directory (<target_directory>/ip/<hdl_subystem>/src), to find a folder named ip_catalog. This folder contains all the necessary files to form an IP from your Model Composer design. The ZIP file, circled below, contains all the files required to include the Model Composer design as IP in the Vivado IP catalog.

Figure 3. ZIP File

Using AXI4 Interfaces

Selecting the Auto Infer Interface option in the IP Catalog Settings dialog box ensures AXI4 interfaces are automatically inferred from the design Gateway In and Gateway Out ports. The Auto Infer Interface option groups signals into AXI4-Stream, AXI4-Lite and AXI4 interfaces based on the port names.

The Auto Infer Interface option will infer interfaces based on the following criteria:

  • The Gateway In and Gateway Out port name suffix must exactly match the signal names in the AXI4 interface standard.
  • The design must contain the minimum number of signals to be considered a valid AXI4 interface.

For example, if a design has two Gateway In ports named PortName_tdata and PortName_tvalid, and also a Gateway Out port named PortName_tready, the Auto Infer Interface option infers these three ports into a single AXI4-Stream port named PortName. In this example.

  • The port name suffixes are exact matches for the signals in an AXI4-Stream interface (TDATA, TREADY and TVALID).
  • These three signals are the minimum signals required for an AXI4-Stream interface.

If optional AXI4 sideband signals are present, for example the TUSER signal is optional in the AXI4-Stream standard, and they are named using the same naming convention (for example, PortName_tuser) they will be grouped into the same AXI4 Interface.

For more details on AXI4 interfaces, AXI4 interface signals names and the minimum required signals for an AXI4 interface, refer to the document Vivado Design Suite: AXI Reference Guide (UG1037).