Hardware Co-Simulation Compilation - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

Vitis Model Composer can compile designs into FPGA hardware that can be used in the loop with Simulink® simulations. This capability is discussed in the topic Using Hardware Co-Simulation.

As shown in the following figure, you can select Hardware Co-Simulation compilation by selecting it from the Export Type menu on the Export tab.

Figure 1. Hardware Co-Simulation

JTAG Hardware Co-Simulation is supported for all AMD development boards.

The Simulink library (<design_name>_hwcosim_lib.slx) generated as part of a Hardware Co-Simulation compilation is placed in the directory you specified in the Export Directory field. This library, and the hardware co-simulation block stored in the library, are described in Hardware Co-Simulation Blocks.