Vitis Model Composer can compile designs into FPGA hardware that can be used in the loop with Simulink® simulations. This capability is discussed in Using Hardware Co-Simulation.
As shown in the following figure, you can select Hardware Co-Simulation compilation by selecting it from the Export Type menu on the Export tab.
All AMD development boards support JTAG Hardware Co-Simulation.
Hardware Co-Simulation compilation generates a Simulink library (<design_name>_hwcosim_lib.slx). This is placed in
the directory you specified in the Export Directory field. Hardware Co-Simulation Blocks describes
this library, and the hardware co-simulation block stored in the
library.