Hardware Design Using the HDL Library - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

Model Composer is a system-level modeling tool that facilitates FPGA hardware design. It extends Simulink® in many ways to provide a modeling environment that is well suited to hardware design. The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through low-level abstractions, allowing the construction of highly efficient FPGA designs.

Table 1. Hardware Design Using the HDL Library
Design Flows Using Model Composer Describes several settings in which constructing designs in Model Composer is useful.
System-Level Modeling in Vitis Model Composer Discusses Model Composer's ability to implement device-specific hardware designs directly from a flexible, high-level, system modeling environment.
Automatic Code Generation Discusses automatic code generation for Model Composer designs using the HDL Library.
Compiling MATLAB into an FPGA Describes how to use a subset of the MATLAB programming language to write functions that describe state machines and arithmetic operators. Functions written in this way can be attached to blocks in Model Composer HDL Library and can be automatically compiled into equivalent HDL.
Importing a Model Composer HDL Design into a Bigger System Discusses how to take the VHDL netlist from a Vitis Model Composer design and synthesize it to embed it into a larger design. Also shows how VHDL created by Model Composer can be incorporated into a simulation model of the overall system.
Variant Subsystems and Vitis Model Composer Explains how to use configurable Subsystems in Model Composer. Describes common tasks such as defining configurable Subsystems, deleting and adding blocks, and using configurable Subsystems to import compilation results into Model Composer designs.
Notes for Higher Performance FPGA Design Suggests design practices in Model Composer that lead to an efficient and high-performance implementation in an FPGA.
Using the FDATool in Digital Filter Applications Demonstrates one way to specify, implement and simulate a FIR filter using the FDATool block.
Multiple Independent Clocks Hardware Design The design can be partitioned into groups of Subsystem blocks, where each Subsystem has a common cycle period, independent of the cycle period of other Subsystems.
AXI Interface Provides an introduction to AMBA AXI4 and draws attention to AMBA AXI4 details with respect to Model Composer
AXI4-Lite Slave Interface Generation Describes features in Vitis Model Composer that allow you to create a standard AXI4-Lite interface for a Model Composer module and then export the module to the AMD Vivado™ IP catalog for later inclusion in a larger design using IP integrator.