Automatic Generation of M-Hwcosim Testbench - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

M-Hwcosim enables the test bench generation for hardware co-simulation. When the Create testbench option is checked in the Model Composer Hub block, the hardware co-simulation compilation flow generates an M-code script (<design>_hwcosim_test.m) and golden test data files (<design>_<port>_hwcosim_test.dat) for each gateway based on the Simulink simulation. The M-code script uses the M-Hwcosim API to implement a test bench that simulates the design in hardware and verifies the results against the golden test data. Any simulation mismatch is reported in a result file (<design>_hwcosim_test.results).

As shown below in the Example, the test bench code generated is easily readable and can be used as a basis for your own simulation code.

Example


				function multi_rates_cw_hwcosim_test
				try
				% Define the number of hardware cycles for the simulation.
				ncycles = 10;
				
				% Load input and output test reference data.
				testdata_in2 = load('multi_rates_cw_in2_hwcosim_test.dat');
				testdata_in3 = load('multi_rates_cw_in3_hwcosim_test.dat');
				testdata_in7 = load('multi_rates_cw_in7_hwcosim_test.dat');
				testdata_pb00 = load('multi_rates_cw_pb00_hwcosim_test.dat');
				testdata_pb01 = load('multi_rates_cw_pb01_hwcosim_test.dat');
				testdata_pb02 = load('multi_rates_cw_pb02_hwcosim_test.dat');
				testdata_pb03 = load('multi_rates_cw_pb03_hwcosim_test.dat');
				testdata_pb04 = load('multi_rates_cw_pb04_hwcosim_test.dat');
				
				% Pre-allocate memory for test results.
				result_pb00 = zeros(size(testdata_pb00));
				result_pb01 = zeros(size(testdata_pb01));
				result_pb02 = zeros(size(testdata_pb02));
				result_pb03 = zeros(size(testdata_pb03));
				result_pb04 = zeros(size(testdata_pb04));
				
				% Initialize sample index counter for each sample period to be 
				% scheduled.
				insp_2 = 1;
				insp_3 = 1;
				insp_7 = 1;
				outsp_1 = 1;
				outsp_2 = 1;
				outsp_3 = 1;
				outsp_7 = 1;
				
				% Define hardware co-simulation project file.
				project = 'multi_rates_cw.hwc';
				
				% Create a hardware co-simulation instance.
				h = Hwcosim(project);
				
				% Open the co-simulation interface and configure the hardware.
				try
				open(h);
				catch
				% If an error occurs, launch the configuration GUI for the user
				% to change interface settings, and then retry the process again.
				release(h);
				drawnow;
				h = Hwcosim(project);
				open(h);
				end
				
				% Simulate for the specified number of cycles.
				for i = 0:(ncycles-1)
				
				% Write data to input ports based their sample period.
				if mod(i, 2) == 0
				h('in2') = testdata_in2(insp_2);
				insp_2 = insp_2 + 1;
				end
				if mod(i, 3) == 0
				h('in3') = testdata_in3(insp_3);
				insp_3 = insp_3 + 1;
				end
				if mod(i, 7) == 0
				h('in7') = testdata_in7(insp_7);
				insp_7 = insp_7 + 1;
				end
				
				% Read data from output ports based their sample period.
				result_pb00(outsp_1) = h('pb00');
				result_pb04(outsp_1) = h('pb04');
				outsp_1 = outsp_1 + 1;
				if mod(i, 2) == 0
				result_pb01(outsp_2) = h('pb01');
				outsp_2 = outsp_2 + 1;
				end
				if mod(i, 3) == 0
				result_pb02(outsp_3) = h('pb02');
				outsp_3 = outsp_3 + 1;
				end
				if mod(i, 7) == 0
				result_pb03(outsp_7) = h('pb03');
				outsp_7 = outsp_7 + 1;
				end
				
				% Advance the hardware clock for one cycle.
				run(h);
				
				end
				
				% Release the hardware co-simulation instance.
				release(h);
				
				% Check simulation result for each output port.
				logfile = 'multi_rates_cw_hwcosim_test.results';
				logfd = fopen(logfile, 'w');
				sim_ok = true;
				sim_ok = sim_ok & check_result(logfd, 'pb00', testdata_pb00, result_pb00);
				sim_ok = sim_ok & check_result(logfd, 'pb01', testdata_pb01, result_pb01);
				sim_ok = sim_ok & check_result(logfd, 'pb02', testdata_pb02, result_pb02);
				sim_ok = sim_ok & check_result(logfd, 'pb03', testdata_pb03, result_pb03);
				sim_ok = sim_ok & check_result(logfd, 'pb04', testdata_pb04, result_pb04);
				fclose(logfd);
				if ~sim_ok
				error('Found errors in simulation results. Please refer to ''%s'' for details.', 
				logfile);
				end
				
				catch
				err = lasterr;
				try release(h); end
				error('Error running hardware co-simulation testbench. %s', err);
				end
				
				%---------------------------------------------------------------------
				
				function ok = check_result(fd, portname, expected, actual)
				ok = false;
				
				fprintf(fd, ['\n' repmat('=', 1, 95), '\n']);
				fprintf(fd, 'Output: %s\n\n', portname);
				
				% Check the number of data values.
				nvals_expected = numel(expected);
				nvals_actual = numel(actual);
				if nvals_expected ~= nvals_actual
				fprintf(fd, ['The number of simulation output values (%d) differs ' ...
				'from the number of reference values (%d).\n'], ...
				nvals_actual, nvals_expected);
				return;
				end
				
				% Check for simulation mismatches.
				mismatches = find(expected ~= actual);
				num_mismatches = numel(mismatches);
				if num_mismatches > 0
				fprintf(fd, 'Number of simulation mismatches = %d\n', num_mismatches);
				fprintf(fd, '\n');
				fprintf(fd, 'Simulation mismatches:\n');
				fprintf(fd, '----------------------\n');
				fprintf(fd, '%10s %40s %40s\n', 'Cycle', 'Expected values', 'Actual values');
				fprintf(fd, '%10d %40.16f %40.16f\n', ...
				[mismatches-1; expected(mismatches); actual(mismatches)]);
				return;
				end
				
				ok = true;
				fprintf(fd, 'Simulation OK\n');