Performing Analysis in Vitis Model Composer - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

Vitis Model Composer is a bit- and cycle-accurate modeling tool. You can verify the functionality of your designs by simulating in Simulink® . However, to ensure that your Model Composer design will work correctly when it is implemented in your target AMD device, these analysis tools have been integrated into Model Composer:

Timing Analysis
To ensure that the HDL files generated by Model Composer operate correctly in hardware, you must close timing. To help accelerate this process, timing analysis has been integrated into Model Composer.
Resource Analysis
To ensure that the HDL files generated by Model Composer will fit into your target device, you might need to analyze the resources being used. To help accelerate this process, resource analysis has been integrated into Model Composer.
Table 1. Performing Analysis in Vitis Model Composer
Presents an overview of timing analysis in Model Composer.
Describes how to perform timing analysis on your model.
Describes how you can cross probe from a row in the Timing Analyzer table to the Simulink model, highlighting the corresponding HDL blocks in the path.
Describes how to re-launch the Timing Analyzer table on pre-existing Timing Analysis results.
Describes methods to help you discover the source of timing violations in your design.
Resource Analysis in Vitis Model Composer Presents an overview of resource analysis in Model Composer.
Describes how to perform resource analysis on your model.
Describes how you can cross probe from a row in the Resource Analyzer table to the Simulink model, highlighting the corresponding block or subsystem in the design.
Describes how to re-launch the Resource Analyzer table on pre-existing Resource Analysis results.
Describes methods to help you use the Resource Analyzer to optimize resource utilization in the design.