Vitis Model Composer is a bit- and cycle-accurate modeling tool. You can verify the functionality of your designs by simulating in Simulink® . However, to ensure your Model Composer design works correctly on your target AMD device, Model Composer provides the following analysis tools:
- Timing Analysis
- To ensure that the HDL files generated by Model Composer operate correctly in hardware, you must close timing. To help accelerate this process, Model Composer includes timing analysis integration.
- Resource Analysis
- To ensure the HDL files from Model Composer fit into your target device, you can analyze the resources using the integrated Resource Analysis tool. To help accelerate this process, Model Composer includes resource analysis integration into Model Composer.
| Presents an overview of timing analysis in Model Composer. | |
| Describes how to perform timing analysis on your model. | |
| Describes how you can cross probe from a row in the Timing Analyzer table to the Simulink model, highlighting the corresponding HDL blocks in the path. | |
| Describes how to re-launch the Timing Analyzer table on pre-existing Timing Analysis results. | |
| Describes methods to help you discover the source of timing violations in your design. | |
| Presents an overview of resource analysis in Model Composer. | |
| Describes how to perform resource analysis on your model. | |
| Describes how you can cross probe from a row in the Resource Analyzer table to the Simulink model, highlighting the corresponding block or subsystem in the design. | |
| Describes how to re-launch the Resource Analyzer table on pre-existing Resource Analysis results. | |
| Describes methods to help you use the Resource Analyzer to optimize resource utilization in the design. |