Configuring Port Types - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

SysgenPortDescriptor provides methods for configuring individual ports. For example, assume port dout is unsigned, 12 bits, with binary point at position 8. The code below shows one way in which this type can be defined.

dout = this_block.port('dout'); 

The following also works:

dout = this_block.port('dout'); 

The first code segment sets the port attributes using individual method calls. The second code segment defines the signal type by specifying the signal type as a string. Both code segments are functionally equivalent.

The black box supports HDL modules with 1-bit ports that are declared using either single bit port (for example, std_logic) or vectors (for example, std_logic_vector(0 downto 0)) notation. By default, Vitis Model Composer assumes ports to be declared as vectors. You can change the default behavior using the useHDLVector method of the descriptor. Setting this method to true tells Model Composer to interpret the port as a vector. A false value tells Model Composer to interpret the port as single bit.

dout.useHDLVector(true); % std_logic_vector 
dout.useHDLVector(false); % std_logic 
Note: The Configuration Wizard automatically sets the port types when it generates a configuration M-function.