Black Box HDL Requirements and Restrictions - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

An HDL component associated with a black box must adhere to the following Vitis Model Composer requirements and restrictions:

  • The entity name must not collide with any other entity name in the design.
  • Bi-directional ports are supported in HDL black boxes, however they will not be displayed in the Model Composer as ports; they only appear in the generated HDL after netlisting.
  • For Verilog black boxes, the module and port names must follow standard HDL naming conventions.
  • Any port that is a clock or clock enable must be of type std_logic. (For Verilog black boxes, ports must be of non-vector inputs, for example, input clk.)
  • Clock and clock enable ports in black box HDL should be expressed as follows: Clock and clock enables must appear as pairs (that is, for every clock, there is a corresponding clock enable, and vice-versa). A black box can have more than one clock port and its behavior changes based on the context of the design.
    • In Synchronous single clock design context, a single clock source is used to drive each clock port. Only the clock enable rates differ.
    • In case of multiple independent hardware clock design context, two different clock sources is used to drive clock and clock enable pins.
  • Each clock name (respectively, clock enable name) must contain the substring clk, for example my_clk_1 and my_ce_1.
  • The name of a clock enable must be the same as that for the corresponding clock, but with ce substituted for clk. For example, if the clock is named src_clk_1, then the clock enable must be named src_ce_1.
  • Falling-edge triggered output data cannot be used.
  • Fixed-point binary values with negative indices (for example, (5 downto -3)) are not supported.
Important: It is not recommended to use the black box block to import encrypted RTLs which are generated for Vivado IP. As an alternative, try to import Vivado IPs using a DCP file.