Vivado Project - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

The HDL Netlist and IP Catalog compilation targets also generate an example Vivado project, which represents an integration of the results of Code Generation.

In the case of the HDL Netlist compilation target, the Vivado project sets the module designed in Vitis Model Composer as the top level and includes instances of IP. Also, if Create testbench is selected in the Vitis Model Composer Hub block, a test bench and stimulus files (*.dat) are also added to the project.

In the case of the IP Catalog compilation target, an example project is created with the following features:

  • The IP generated from Model Composer is already added to the IP catalog associated with the project and available for the RTL flow as well as the IP integrator-based flow.
  • The design includes an RTL instantiation of IP called <ip>_0 underneath <design>_stub that indicates how to instantiate such an IP in the RTL flow
  • The design includes an RTL test bench called <design>_tb that also instantiates the same IP in the RTL flow.
Note: A test bench is not created if AXI4-Lite slave interface generation is selected in a Gateway In or Gateway Out block.
  • The project also includes an example IP integrator diagram with a Zynq 7000 subsystem if the part selected in this example is a Zynq 7000 SoC part. For all other parts, a MicroBlazeâ„¢ -based subsystem is created.