This topic discusses the low-level files Vitis Model Composer produces when HDL
Netlist is the selected Export Type and Export is clicked in the Model Composer Hub block. The
files consist of HDL that implements the design. In addition, Model Composer organizes the HDL
files, and other hardware files into an AMD Vivado™
IDE
Project. These files are written to the folder <target
directory>/ip/<design_name>/src where <target
directory> is the target directory specified on the Model Composer Hub block. If
no test bench is requested, then the key files produced by Model Composer are the
following:
| File Name or Type | Description |
|---|---|
sysgen/<design_name>.vhd/.v
|
This file contains a hierarchical structural netlist along with clock/clock enable controls |
sysgen/<design_name_entity_declarations>.vhd/.v
|
This file contains the entity of module definitions of HDL blocks in the design. |
hdl_netlist/<design_name>.xpr
|
This file is the Vivado IDE project file that describes all of the attributes of the Vivado IDE design. |
If a test bench is requested, then, in addition to the above, Model Composer produces files that allow simulation results to be compared. The comparisons are between Simulink® simulation results and corresponding results from Questa, or any other RTL simulator supported by AMD Vivado™ IDE such as Vivado simulator, or VCS. The additional files are as follows:
| File Name or Type | Description |
|---|---|
| Various .dat files | These contain the simulation results from Simulink. |
sysgen/<design_name>_tb.vhd/.v
|
This is a test bench that wraps the design. When simulated, this test bench compares simulation results from the digital simulator against those produced by Simulink. |