Design Considerations - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English
  • HDL and HLS subsystems can only have AXI4-Stream input and output ports. The AXI4-Stream input and output ports of the subsystem must have a bit width that is a multiple of 8 bits, up to a maximum of 128 bits.
  • Ensure that there are no extra outputs from the subsystem that will not be in the hardware implementation, such as debug outputs to monitor internal signals.
  • If multiple blocks are being driven by the same input signal, the signal multiplexing must occur outside the hardware subsystem, so there are subsystem inputs for each block input.
  • Considerations for HLS Designs:
    • You can only use HLS Kernel blocks to import HLS C/C++ code (for PL). The blocks from the HLS library are not supported by the Hardware Validation Flow
    • The HLS Kernel should be in free-running mode. This is accomplished by the including the following pragma in the HLS function: #pragma HLS INTERFACE ap_ctrl_none port=return
    • The port name in the function signature must match in both the header file and the source file.
    • Ensure the bit width of the HLS Kernel input or output that connects with the AI Engine matches the PLIO width of the AIE.
  • If any of the design inputs are randomized between simulation runs, the design might appear to fail verification. To resolve this issue, set the seed of MATLAB's random number generator to a fixed value (for example, rng(1)) before generating input data.