Generating C++ Code - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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Release Date
2024.1 English

The following figure shows the HLS C++ Code output by Vitis Model Composer from the Export command. The C++ code is output either as an intermediate step when exporting a packaged IP for Vivado output, or as a specified Export Type to let you optimize the C++ code using directives or pragmas in AMD Vitis™ HLS.

Figure 1. C++ Output Files

The files generated by Model Composer reflect the contents and hierarchy of the subsystem that was compiled. In this case, the subsystem is the Edge Detection function described in the HLS section of the Vitis Model Composer Tutorials. The following figure shows the contents of the Edge Detection subsystem.

Figure 2. Edge Detection Subsystem Generated by Your Tool
The Edge_Detection.cpp file specifies the following include files, which incorporate the code generated for the various Model Composer blocks used in the subsystem:
#include "Edge_Detection.h"
#include "GradMagnitude.h"
#include "SobelFilter.h"

The following shows the generated code for the Edge Detection subsystem. Notice the pragmas added to the function to specify the function protocol and the I/O port protocols for the function signature and return value. The pragmas help direct the solution synthesized by Vitis HLS, and result in higher performance in the implemented RTL.

Edge_Detection(hls::stream< ap_axiu<16, 1, 1, 1> >& Y, 
    hls::stream< ap_axiu<16, 1, 1, 1> >& Y_Out)
    #pragma HLS INTERFACE s_axilite port=return
    #pragma HLS INTERFACE axis bundle=image_out port=Y_Out
    #pragma HLS INTERFACE axis bundle=input_vid port=Y
    #pragma HLS dataflow
    uint8_t core_Y[360][640];
    #pragma HLS stream variable=core_Y dim=2 depth=1
    uint8_t core_Cb[360][320];
    #pragma HLS stream variable=core_Cb dim=2 depth=1
    uint8_t core_Cr[360][320];
    #pragma HLS stream variable=core_Cr dim=2 depth=1
    uint8_t core_Y_Out[360][640];
    #pragma HLS stream variable=core_Y_Out dim=2 depth=1
    uint8_t core_Cb_Out[360][320];
    #pragma HLS stream variable=core_Cb_Out dim=2 depth=1
    uint8_t core_Cr_Out[360][320];
    #pragma HLS stream variable=core_Cr_Out dim=2 depth=1
    fourier::AxiVideoStreamAdapter< uint8_t >::readStreamVf0(Y, 
        reinterpret_cast< uint8_t* >(core_Y), reinterpret_cast< uint8_t* >(
        core_Cb), reinterpret_cast< uint8_t* >(core_Cr), 360, 640);
    Edge_Detection_core(core_Y, core_Cb, core_Cr, core_Y_Out, core_Cb_Out, 
    fourier::AxiVideoStreamAdapter< uint8_t >::writeStreamVf0(Y_Out, 
        reinterpret_cast< uint8_t* >(core_Y_Out), reinterpret_cast< uint8_t* >(
        core_Cb_Out), reinterpret_cast< uint8_t* >(core_Cr_Out), 360, 640);

Finally, notice the various Tcl scripts generated in the output folder. They can be used to automate various packaging, synthesis and simulation steps in Vitis:

  • run_hls.tcl: This is a Tcl script that can be used to run Vitis HLS on the generated output files to create a Vitis HLS project and solution. Each Vitis HLS project holds one set of C/C++ code and can contain multiple solutions. Each solution can have different constraints and optimization directives. For more information refer to the Vitis High-Level Synthesis User Guide (UG1399).
  • run_hls_csim.tcl: Same as run_hls.tcl, but also runs C simulation of the solution.
  • run_hls_rtlcosim.tcl: Same as run_hls_csim.tcl, but also synthesizes RTL code from the C++ code and runs RTL simulation of the solution.
  • run_hls_exportasip.tcl: Same as run_hls_rtlcosim.tcl, but also generates an IP from the solution.

You can run the Tcl scripts from an AMD Vitis™ HLS command prompt as follows:

  1. Open the AMD Vitis™ HLS Command Prompt:
    • On Windows, click Start > All Programs > Xilinx Design Tools > Vitis HLS 2024.1 > Vitis HLS > Vitis HLS 2024.1 Command Prompt.
    • On Linux, open a new shell and source the <install_dir>/Vitis_HLS/<version>/ script to configure the shell.
  2. From the command prompt, change the directory to the parent folder of the Export Directory specified on the Model Composer Hub dialog box when you generated the output, as discussed at Vitis Model Composer Hub.
  3. Further change directory into the src folder containing the Tcl scripts. For example:
    cd ip/edge_detection/src
  4. From the command prompt, launch the run_hls.tcl script:
    vitis-run --mode hls --tcl ./run_hls.tcl

AMD Vitis™ HLS launches to synthesize the RTL from the C++ code, generating an AMD Vitis™ HLS project, and solution in the process.