Debugging Clock Propagation - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

The Model Composer Hub block can be used to control the display of all HDL Block Icons using the Block Icon Display control in the HDL Analyze tab. From this tab, you can either select Normalized sample periods or Sample frequencies to help understand how clocks get propagated in the design. For multiple clock designs, the behavior of Normalized sample periods is that the smallest Simulink system period is used to normalize all the sample periods in the design.

For Sample Frequencies, the port icon text display is the result of the following computation:

(1e6/FPGA clock period) * Simulink system period/Port sample period

where FPGA clock period is the FPGA clock period specified in ns in the domain’s Clock Settings tab, and Simulink system period is the Simulink system period in seconds specified in the domain’s HDL Clock Settings tab.

To ensure that the simulation models the hardware behavior relatively with respect to the clocks, the ratio of Simulink system period to FPGA clock period in each domain must be the same. If this relationship is not complied with the correct ratio, a warning is thrown to indicate this problem as shown in the following figure:

Figure 1. Warning