SysgenPortDescriptor Methods - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English
Method Description
setName(name) Sets the HDL name to be used for this port.
setSimulinkPortNumber(num) Sets the index associated with this port in SimulinkĀ® . num tells the index to assign. Indexing starts with 1 (as in Simulink).
setType(typeName)

Sets the type of this port to type. Type must be one of Bool, UFix_<n>_<b> , Fix_<n>_<b> , signed or unsigned. The last two choices leave the width and binary point position unchanged.

XFloat_<exponent_bit_width>_fraction_bit_width> is also supported. For example: ap_return_port = this_block.port('ap_return');

ap_return_port.setType('XFloat_30_2');

setWidth(w) Sets the width of this port to w.
setBinpt(bp) Sets the binary point position of this port to bp.
makeBool() Makes this port Boolean.
makeSigned() Makes this port signed.
makeUnsigned() Makes this port unsigned.
setConstant() Makes this port constant
setGatewayFileName(filename) Sets the dat file name that will be used in simulations and test-bench generation for this port. This function is only meant for use with bi-directional ports so that a hand written data file can be used during simulation. Setting this parameter for input or output ports is invalid and will be ignored.
setRate(rate) Assigns the rate for this port. rate must be a positive integer expressed as a MATLABĀ® double or Inf for constants.
useHDLVector(s) Tells whether a 1-bit port is represented as single-bit (ex: std_logic) or vector (ex: std_logic_vector(0 downto 0)).
HDLTypeIsVector() Sets representation of the 1-bit port to std_logic_vector(0 downto 0).