Example 2: Creating a Bitstream Target - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English
  1. Open a Vitis Model Composer design.
  2. In the MATLAB command Window, modify the path as per your requirements, similar to the first example, and then enter the following command:
    xilinx.environment.addCompilationTarget('Bitstream', '.')
    

    This provides a template derived class for the users to edit. The last field corresponds to the directory which contains the board.xml file.

  3. In the MATLAB Command Window, enter the following command:
    xilinx.environment.rehashCompilationTarget
    

    This will ensure that the new compilation target is picked up by the Vitis Model Composer Hub block.

  4. Close and then re-open the Vitis Model Composer Hub block.
  5. You will now see the compilation target Bitstream on the Vitis Model Composer Hub block.
  6. Open the Bitstream.m created in the './Bitstream/@Bitstream/Bitstream.m'.
  7. Download the following two files:

  8. Inside the function pre_project_creation(), add the following lines to do the following:
    1. Set the board as a KC705 board.
    2. Add a new top-level file (top.v) to use the differential clock ports of KC705.
    3. Add a new XDC file to give the location constraints for the clock, dip, and led ports.
    4. Set the newly added module top as the top.
    5. Run synthesis.
    6. Run implementation.
    7. Generate bitstream.

    After you save the files to a location on your computer, you should give the full path to the files in the add_file API as per your path.

    add_tcl_command(obj, 'set_property board xilinx.com:kintex7:kc705:1.1 
    [current_project]');
    add_file(obj, 
    '/group/dspusers-xsj/umangp/rel/2013.4/cust_comp_test/bitstream_example.xdc');
    add_file(obj, '/group/dspusers-xsj/umangp/rel/2013.4/cust_comp_test/top.v');
    obj.top_level_module = 'top';
    run_synthesis(obj);
    run_implementation(obj);
    generate_bitstream(obj); 
    
  9. In the MATLAB Command Window, enter the following command:
    xilinx.environment.rehashCompilationTarget
    

    This ensures that the new compilation target is picked up by the Vitis Model Composer Hub block.

  10. Close and then re-open the Vitis Model Composer Hub block.
  11. Select the Bitstream compilation target.
  12. Click the Generate button.
  13. After the generation is complete, you can find the bit file in the following directory:
    ./<target_directory>/ip/<hdl_subystem>/src/Bitstream/bitstream_example.runs/impl_1/top.bit