AIE to HDL - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

The AIE to HDL block connects the output of AI Engine block with the input of HDL block. This block accepts variable size signal from AI Engine blocks along with the tready signal which indicates whether the HDL domain can accept the data. The input data type to this block is inherited from the input signal. Note that if the HDL domain tready signal stays low for a long time, eventually the internal buffers in the AIE to HDL block will overflow and the simulation stops. The bit width of the tdata output of the AIE to HDL block is limited to 32, 64, and 128 according hardware functionality.

Figure 1. AIE to HDL
Figure 2. AIE to HDL Parameters