Burst Data Transfer Mode - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

If you enable burst data transfer mode in the Vitis Model Composer Hub block, the non-clock input and output registers will be replaced with "n"-entry FIFOs. You can select "n" (FIFO depth), which is useful for trading off performance versus FPGA block RAM resource use.

Figure 1. Burst Mode

Enabling Burst Mode allows the M-HWCosim scheduler to "burst write" a time-sequence of "n" values into each input FIFO, run the clock for a number of cycles determined by the rate of input/output ports and the FIFO depths, and capture the resulting output in the output FIFOs. After the batch has been run, the scheduler proceeds to "burst read" the contents of the output FIFOs into a MATLAB array, where it can be checked against expected data.

Figure 2. Burst Mode Flow

This batch processing of time samples allows to better pack data into JTAG sequences or thereby significantly reducing overhead.