Setting the HDL-AIE Block - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

The following image depicts the components that are needed to connect an HDL design to an AI Engine subsystem. In setting this connection, you should consider certain input design criteria and set the parameters of the blocks accordingly. These input design criteria are:

  1. The output data type from the HDL design (DT1). The width (W) of DT1 should be 32, 64, or 128 bits for an AXI-S signal.
  2. The input data type to the AI Engine kernel block (DT2). This is determined by the AI Engine kernel.
  3. The number of samples in the input to the AI Engine kernel block (S). For an AI Engine kernel with a window input type this is typically the size of the input window. For an AI Engine kernel with a stream input, this is typically the number of samples the AI Engine kernel consumes at every invocation.
  4. If the HDL design only produces a new sample every N clock cycles, the output sample rate can be reduced by an optional factor N.
Figure 1. Setting the HDL to AIE Block

Considering the five design criteria above, set the parameters of the blocks as follows:

Step 1: Set the PLIO bit width in the PLIO block

Set the PLIO bit width to W.

Step 2: Set the parameters of the HDL to AIE block

  • Set Input data type to DT1.
  • Set Output data type to DT2.
  • Set Number of output samples to S.
  • Set Reduce output sample rate by a factor of to N.

Step 3: Set the Gateway Out AXIS block

Set the Sample Period parameter to the same value as in the corresponding Gateway In AXI4-Stream block.