Clock Propagation Algorithm - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

For all HDL blocks in the src_domain, the clocking is governed by the Clock 1 tab in the Model Composer Hub block. Similarly for the dest_domain Subsystem, the clocking is governed by the Clock 2 tab in the Model Composer Hub block. For the FIFO block, the clocks are derived from its context in the design. Because the we and din ports are driven by signals emanating from the src_domain Subsystem, the wr_clk of the FIFO is tied to the src_domain clock. Because the dout, full, and re ports either drive or load signals from dest_domain, the rd_clk of the FIFO is tied to the dest_domain clock. Mixing and matching these signals across clock domains or using any other block (other than FIFO or Dual Port RAM) to cross clock domains will result in a DRC error.