Integration Design Rules - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

When a Vitis Model Composer model is to be included into a larger design, the following two design rules must be followed.

Rule 1
No Gateway should specify an IOB/CLK location.

IOB timing constraints should be set to: none.

Rule 2
If there are any I/O ports from the Model Composer design that are required to be ports on the top-level design, appropriate buffers should be instantiated in the top-level HDL code.