Importing HDL Modules - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

Sometimes it is important to add one or more existing HDL modules to a Vitis Model Composer design. The HDL Black Box block allows VHDL and Verilog to be brought into a design. The Black Box block behaves like other Model Composer HDL blocks - it is wired into the design, participates in simulations, and is compiled into hardware. When Model Composer compiles a Black Box block, it automatically connects the ports of the Black Box to the rest of the design. A Black Box can be configured to support either synchronous clock designs or multiple hardware clock designs based on the context and Model Composer Hub block settings.

Table 1. Black Box Interface
Black Box HDL Requirements and Restrictions Details the requirements and restrictions for VHDL, Verilog, and EDIF associated with black boxes.
Black Box Configuration Wizard Describes how to use the Black Box Configuration Wizard.
Black Box Configuration M-Function Describes how to create a black box configuration M-function.
Table 2. HDL Co-Simulation
Configuring the HDL Simulator Explains how to configure the AMD Vivado™ simulator or Questa to co-simulate the HDL in the Black Box block.
Co-Simulating Multiple Black Boxes Describes how to co-simulate several Black Box blocks in a single HDL simulator session.