Vitis Model Composer Hub Block Parameters - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English
Table 1. Hardware Selection Tab
Field in the App Parameter Name Allowed Values
Select Hardware SelectHardware Part, or board name or platform file
Table 2. Subsystem Selection
Field in the App Parameter Name Allowed Values Notes
To select the subsystem in the left side panel SelectSubsystem 0 or 1  
TargetSubsystem   Read-only parameter. Returns list of subsystems that are selected for the code generation
Table 3. Settings Tab
Field in the App Parameter Name Allowed Values Notes
Hardware Description HardwareDescription
  • Verilog
  • VHDL
 
  VHDLLibrary String or Char array  
  UseSTDLogic 0 or 1  
Synthesis Strategy SynthesisStrategy String or Char array (should be a valid synthesis strategy).  
Implementation Strategy ImplementationStrategy String or Char array (should be a valid implementation strategy).  
Enable Multiple clocks EnableMultipleClocks 0 or 1  
FPGA Clock Period FPGAClockPeriod String or Char array (Ex: '10')  
Simulink System Period SimulinkSystemPeriod String or Char array (Ex: '1')  
Clock pin location ClockPinLocation String or Char array  
Provide Clock enable clear pin ProvideClockEnableClearPin 0 or 1  
  ClockSettings Struct with the fields:
  • subsystem
  • fpgaClockPeriod
  • simulinkSystemPeriod
  • clockPinLocation
  • provideClockEnableClearPin
 
FPGA Clock Frequency FPGAClockFrequency String or Char array (Ex: '200')  
Throughput factor ThroughputFactor 0 to 9  
Testbench stack size TestbenchStackSize String or Char array (Ex: '10')  
AIE Compiler Options AIECompilerOptions Cell array of character vectors or an empty cell array.  
Table 4. Analyze Tab
Field in the App Parameter Name Allowed Values  
Block Icon Display BlockIconDisplay
  • Default
  • Normalized sample periods
  • Sample frequencies (MHz)
  • Pipeline stages
  • HDL port names
  • Input data types
  • Output data types
 
Perform Analysis PerformAnalysis
  • None
  • Post Synthesis
  • Post Implementation
 
Analysis Type AnalyzerType
  • Timing
  • Resource
 
Remote IP Cache RemoteIPCache 0 or 1  
Create Interface document CreateInterfaceDocument 0 or 1  
AIE Simulator Options AIESimulatorOptions Cell array of character vectors or an empty cell array.  
Simulation Timeout SimulationTimeout String or Char array  
Plot AIE simulation output and Estimate throughput PlotAIESimulation 0 or 1  
Collect Profiling Statistics CollectProfilingStats 0 or 1  
Collect Data for Vitis Analyzer CollectDataForVitisAnalyzer 0 or 1  
Table 5. Validate on Hardware Tab
Field in the App Parameter Name Allowed Values
Generate Hardware Validation Code GenerateHwValidationCode 0 or 1
Generate Hardware Image GenerateHwImage 0 or 1
Target Directory ValidateOnHardwareTargetDirectory Directory
HW System Type HwSystemType
  • BareMetal
  • Linux
Target HwTarget
  • hw
  • hw_emu
Common SW Dir HWCommonSWDir Directory
Target SDK Dir TargetSDKDir Directory
Table 6. Export Tab
Field in the App Parameter Name Allowed Values  
Export Directory ExportDirectory Directory  
Export Type ExportType String or Char array  
Create Testbench CreateTestbench 0 or 1  
Vendor IPVendor String or Char array IP catalog Settings
Library IPLibrary String or Char array
Name IPName String or Char array
Version IPVersion String or Char array
Category IPCategory String or Char array
Status IPStatus
  • 1 for Production
  • 2 for Beta
  • 3 for Pre-production
Auto Infer Interface IPAutoInferInterface 0 or 1
Use Common repository directory (Checkbox) IPUseCommonRepoDir 0 or 1
Edit field beside Use Common repository directory checkbox IPCommonRepoDir String or Char array
Use plug-in project IPUsePlugInProject 0 or 1
Hardware description language (for HLS IP) IPHwDescLang
  • Verilog
  • VHDL
Burst Mode HwCosimBurstMode 0 or 1 Hardware Co-simulation Settings
FIFO HwCosimFifoDepth
  • 1024
  • 2048
  • 4096
  • 8192
Table 7. Design Settings Tab
Field in the App Parameter Name Allowed Values
Treat this model as a legacy System Generator design for backward-compatibility TreatDesignAsLegacyHDL 0 or 1
Number of parallel AI Engine builds NumOfAIEParallelBuilds range (1, number of cores in the system)