This Black Box feature allows you to import VHDL modules that have predefined library dependencies. The following example illustrates how to do this import.
The VHDL module below is a 4-bit, Up counter with asynchronous clear (async_counter.vhd). It compiles into a library named async_counter_lib.
The VHDL module below is a 4-bit, Up counter with synchronous clear
(sync_counter.vhd). It is compiled into a
library named sync_counter_lib.
The VHDL module below is the top-level module that is used to instantiate the previous modules. This is the module that you need to point to when adding the Black Box into your Model Composer model.
The VHDL is imported by first importing the top-level entity, top_level, using the Black Box.
After importing the file, you need to midify the associated Black Box Configuration M-file as follows:
The interface function addFileToLibrary
specifies a library name other than “work” and instructs the tool to compile the
associated HDL source to the specified library.
The Model Composer model looks similar to the following figure.
The next step is to double-click the Model Composer Hub block and click the Generate button to generate the HDL netlist.
The generation process creats a Vivado IDE project (.xpr). This is placed with the
hdl_netlist folder under the netlist folder. Double-clicking the Vivado IDE project and selecting the
Libraries tab under the
Source view displays the work library, and also an async_counter_lib and sync_counter_lib
library.