Vitis Model Composer for AI Engine Development - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

AMD Vitis™ Model Composer enables the rapid simulation, exploration, and code generation of algorithms targeted for AI Engines from within the Simulink® environment. You can achieve this by importing AI Engines kernels and data-flow graphs into Model Composer as blocks and controlling the behavior of the kernels and graphs by configuring the block GUI parameters. Simulation results can be visualized by seamlessly connecting Simulink source and sink blocks with the Model Composer AI Engines blocks. Furthermore, the simulation results can be sent to the MATLAB® workspace for further analysis.

Refer to Creating an AI Engine Design using Vitis Model Composer for more information on importing AI Engine kernels and graphs as blocks.

Vitis Model Composer provides a set of AI Engine library blocks for use within the Simulink environment. These include:

  • Blocks that support importing AI Engine kernel or graph code into Simulink.
  • Blocks that support connection between the AI Engine and the AMD HDL blockset.
  • Configurable AI Engine blocks for DSP functions such as FIRs, FFTs, Mixers, and DDS.
Note: For more information on specific blocks refer to the AMD Vitis™ Model Composer AI Engine Block library.

Connecting HLS kernel blocks, HDL library blocks, and AI Engine blocks, allows modeling and simulation of a heterogeneous platform which can be targeted to both programmable logic and AI Engines in AMD Versal™ Adaptive SoC devices.

Vitis Model Composer supports targeting both AIE and AIE-ML devices. Vitis Model Composer supports features specific to the AIE-ML architecture, including memory tile shared buffers and the bfloat16 data type.

In addition to simulation, you can also use the AI Engine Model Composer Hub to generate dataflow graphs. For more details on the AI Engine Model Composer Hub block, specific to AI Engine code generation, refer to Code Generation.

AI Engine Model composer allows you to verify the generated dataflow graph code using the AI Engine simulator. Based on verification requirements, you can choose to verify your algorithm from the Hub block.

The simulation results are compared against the reference design in the Simulink environment.
Note: Refer to Simulation and Code Generation for more details on simulator options and verification.

A typical AI Engine design flow is shown in the following diagram.

Figure 1. Typical AI Engine Design Flow

To learn more about the AI Engine flow in Model Composer, refer to the Vitis Model Composer Tutorials.

The remainder of this section discusses the following topics: