Notes for Higher Performance FPGA Design - 2025.2 English - UG1483

If you focus all optimization efforts on back-end implementation tools, you might fail to achieve timing closure for the following reasons:

• The more complex IP blocks in a Model Composer design like FIR Compiler and FFT are generated 'under the hood'. These are provided as highly-optimized netlists to the synthesis tool and the implementation tools, so further optimization might not be possible.
• Model Composer netlisting produces HDL code with many instantiated primitives such as registers, block RAMs, and DSP48E1s. There is not much a synthesis tool can do to optimize these elements.

The following tips focus on what you can do in Model Composer to increase the performance of your design before you start the implementation process.

• Review the Hardware Notes Included with Each Block Dialog Box
• Register the Inputs and Outputs of Your Design
• Insert Pipeline Registers
• Use Saturation Arithmetic and Rounding Only When Necessary
• Set the Data Rate Option on All Gateway Blocks
• Pipeline for Maximum Performance
• Other Things to Try