Specifying PLIO Frequency - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2024.1 English

The AI Engine can run at up to 1.25 GHz and can write (at most) two streams with a 32-bit data width per cycle. In contrast, an IP implemented in the PL can run at up to 500 MHz, while consuming a larger bit-width. In order to balance the throughput between the AI Engine and PL, and also ensure the processes do not create a bottleneck with respect to the total performance, it is required to match the rates between the two. Vitis Model Composer supports specifying the frequency of PL from Platform I/O tab in AIE Signal Spec block.

You can either adjust the PLIO frequency or the Width to match the rate between the AI Engine and PL. Consider an example of a 32-bit channel written to each cycle by the AI Engine at 1 GHz. In order for PL to match the rate of AI Engine, it has to consume twice the data at half the frequency or four times the data at a quarter of the frequency.

Table 1. PLIO Frequency
AI Engine PL
Frequency Data per Cycle Frequency Data per Cycle
1 GHz 32 bit 500 MHz 64 bit
    256 MHz 128 bit