Pipeline for Maximum Performance - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

For Vitis Model Composer HDL blocks that use AMD LogiCOREā„¢ IP internally, the default tool behavior is to place at least one register outside of the core. For latency values greater than the optimum value of the core, the optimal pipeline registers are placed inside the core, and the remainder of the registers get pushed out.