Recommendations For Troubleshooting Timing Violations - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

The following are recommended for troubleshooting timing violations:

  • For quicker timing analysis iterations, post-synthesis analysis is preferred over post-implementation analysis.
  • After logic optimization during the Vivado Synthesis process the tool doesn't keep information about merged logic in the Vivado database. Merged and shared logic can make it difficult to accurately cross probe from Vivado timing paths to the Simulink model. Hence, it is recommended that you create a custom Vivado Synthesis strategy to control merged and shared logic.

For information about how to create a custom Synthesis strategy in Vivado, see this link in the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).

To control merged and shared logic in the Vivado IDE, make the following changes to the default Vivado Synthesis strategy.

  1. Set these Synthesis options in Vivado IDE:
    • Select the Synthesis option -keep_equivalent_registers.
    • Set the Synthesis option -resource_sharing to the value off.
  2. Save the new Synthesis strategy and exit Vivado IDE.
  3. In Model Composer, select the new custom Synthesis strategy in the Model Composer Hub dialog box before generating the design.