When translated into hardware, Vitis Model Composer's HDL Gateway In and Gateway Out blocks become input and output ports. The locations of these ports and the speeds at which they must operate can be entered in the Gateway In and Out parameter dialog boxes. Port location and speed are specified in the constraints file by IOB timing.
This topic describes how Model Composer handles hardware clocks in the HDL it
generates. Assume the design is named <design>, and <design> is an acceptable HDL
identifier. When Model Composer compiles the design, it writes a
collection of HDL entities or modules, the topmost of which is
named <design>, and is
stored in a file named <design>.vhd/.v.