Configuring the Vitis Model Composer Hub Block - 2024.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
UG1483
Release Date
2024-05-30
Version
2024.1 English

The Vitis Model Composer Hub block has to be configured to indicate that the Code Generation must proceed for a multiple clock design. This is indicated by turning on the Enable multiple clocks check box on the HDL Settings tab. This indicates to the Code Generation engine that the clock information for the Subsystems src_domain and dest_domain must be obtained from each clock's sub-tab. If this check box is not enabled, then the design will be treated as a single clock design.