AXI4-Lite Interface Synthesis in Vitis Model Composer - 2024.1 English

Vitis Model Composer User Guide (UG1483)

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2024.1 English

Design creation and verification is exactly the same as any other Vitis Model Composer design that does not include an AXI4-Lite interface. Consider the example_dds design shown below.

Figure 1. Example DDS Design

This design contains a DDS Compiler where the two input ports, config_tvalid and config_tdata_pinc are used to control the output frequency.

Following are the simulation results of this design which indicate both sine and cosine output separately.

Figure 2. Simulation Results