When Vivado synthesis is invoked by Vitis Model Composer, a disk cache is used to speed up the iterative design process.
Vivado synthesis is invoked when performing Timing or Resource analysis or when exporting a Synthesized Checkpoint.
With the cache enabled for your design, whenever your compilation generates an IP instance for synthesis, and the Vivado synthesis tool creates synthesis output products, the tools create an entry in the cache area.
After the cache is populated, when a new customization of the IP is created which has the exact same properties, the IP is not synthesized again; instead, the cache is referenced and the corresponding synthesis output in the cache is copied to your design's output directory. Because the IP instance is not synthesized again, and this process is repeated for every IP referenced in your design, generation of the output products is completed more quickly.
The IP cache is shared across multiple Simulink models on your system. If you reuse an IP in one design by including it in another design, and the IP is customized identically and has the same part and language settings in both Simulink models, you can gain the benefit of caching when you compile either of the designs.
To find the location of the IP cache directory on your system, enter the
command xilinx.environment.getipcachepath on the
MATLAB command line. The full path to the IP
cache directory will display in the MATLAB command
window.
>> xilinx.environment.getipcachepath
ans =
C:/Users/your_id/AppData/Local/Xilinx/Sysgen/SysgenVivado/win64.o/ip
IP caching in Model Composer is similar to IP caching in the Vivado Design Suite, described at this link in the Vivado Design Suite User Guide: Designing with IP (UG896). However, the IP cache for Model Composer designs is in a different location than the IP cache for Vivado projects.