Vitis Model Composer Hub - 2022.1 English

Control implementation of the model.

Description

The Vitis Model Composer Hub block controls the behavior of the Vitis Model Composer tool.

You can specify the targeted design flow for the generated output, the directory path for the output, and the desired device and design clock frequency using the following tabs.

• The Target pane helps with device or board selection.
• The AI Engine pane specifies options that control the AI Engine code generation flow.
• The HDL pane specifies options that control the HDL code generation flow. (These options are same as the legacy System Generator Token.)
• The HLS pane specifies options that control the HLS code generation flow.
• The Hardware Flow pane specifies options required for validating the design on the hardware.
• The Generate pane provides options to select the output flow by selecting subsystems and specifying Code directory.

Library

AI Engine/Tools; HLS/Tools; Utilities/Code Generation.

Data Type Support

Data type support is not applicable to the Vitis Model Composer Hub block.

Parameters

The following section describes the configurable options available in each pane of the Vitis Model Composer Hub block.

Target

Select Hardware:

• Clicking the browse button (…) displays the Device Chooser dialog box. This allows you to select a part, board, or platform to which your design is targeted. Vitis Model Composer obtains board and device data from the Vivado database.

HLS

Target Subsystem:

• Select the subsystem name from the drop-down menu that needs to be targeted for HLS code generation.

HLS/Settings

Target:

Target settings are shown in the following table.

Table 1. HLS Target Settings

Setting	Description
IP Catalog	Select IP Catalog to export the design to the Vivado IP Catalog. After C/C++ code generation, Vitis High-Level Synthesis (HLS) is invoked to synthesize the C code and create a project that can be exported as an IP to the Vivado IP Catalog.
System Generator	Select System Generator to export the design to HDL blockset. After C/C++ code generation, Vitis High-Level Synthesis (HLS) is invoked to synthesize the C code and create an RTL solution that can be used as a Vitis HLS block in a HDL model.
HLS C++ Code	Select HLS C++ code to compile the design model into C++ code.

FPGA clock frequency:

• Specifies the clock frequency in MHz for the targeted device. This frequency is passed to the downstream tool flow.

Throughput factor:

• Specifies the number of samples processed per clock to increase the throughput. A larger factor increases hardware resource usage. The throughput factor must be between 1 and 16.

Create testbench and run C simulation:

• If selected, Vitis Model Composer runs simulation and generates test vectors while generating code.

Testbench stack size (MBytes):

• This parameter prompts you to enter a larger stack size. When Create and run testbench is enabled, the Testbench stack size option specifies the size of the testbench stack frame during C simulation (CSIM). Occasionally, the default stack frame size of 10 MB allocated for execution of the testbench may be insufficient to run the test, due to large arrays allocated on the stack and/or deep nesting of sub-systems. Typically when this happens, the test would fail with a segmentation fault and an associated error message. In such a case you may opt to increase the size of the stack frame and rerun the test.

Generate

Select a Subsystem containing blocks from the AI Engine, HDL, or HLS blocksets and specify the corresponding Code Directory. The Code Directory can be specified by entering the complete directory path or using the Browse button to provide a path.