Control implementation of the model.
Description
The Vitis Model Composer Hub block controls the behavior of the Vitis Model Composer tool.
You can specify the targeted design flow for the generated output, the directory path for the output, and the desired device and design clock frequency using the following tabs.
- The Target pane helps with device or board selection.
- The AI Engine pane specifies options that control the AI Engine code generation flow.
- The HDL pane specifies options that control the HDL code generation flow. (These options are same as the legacy System Generator Token.)
- The HLS pane specifies options that control the HLS code generation flow.
- The Hardware Flow pane specifies options required for validating the design on the hardware.
- The Generate pane provides options to select the output flow by selecting subsystems and specifying Code directory.
Library
AI Engine/Tools; HLS/Tools; Utilities/Code Generation.
Data Type Support
Data type support is not applicable to the Vitis Model Composer Hub block.
Parameters
Figure 1.
Vitis Model Composer Hub Block
Parameters

The following section describes the configurable options available in each pane of the Vitis Model Composer Hub block.
- Target
-
Select Hardware:
- Clicking the browse button (…) displays the Device Chooser dialog box. This allows you to select a part, board, or platform to which your design is targeted. Vitis Model Composer obtains board and device data from the Vivado database.
- AI Engine
-
Target Subsystem:
- Select the subsystem name from the drop-down menu that needs to be targeted for AI Engine code generation.
- AI Engine/Settings
-
Compiler options:
- When enabled, this option provides control over compiler debug options, execution target options etc.
- HDL
-
Target Subsystem:
- Select the subsystem name from the drop-down menu that needs to be targeted for HDL code generation.
- HDL/Settings
-
Compilation Type::
- Specifies the type of compilation result that should be produced when the code generator
is invoked. The default compilation type is IP Catalog.The Settings button is activated when one of these compilation types is selected:
- IP Catalog compilation: The Settings button brings up a dialog box that allows you toadd a description of the IP that will be placed in the IP catalog.
- Hardware Co-Simulation (JTAG) compilation: The Settings button brings up a dialog box that allows you to use burst data transfers to speed up JTAG hardware co-simulation.
- Specifies the type of compilation result that should be produced when the code generator
is invoked. The default compilation type is IP Catalog.
- HDL Clocking
-
FPGA clock period (ns):
- Defines the period in nanoseconds of the system clock. The value need not be an integer. The period is passed to the Xilinx implementation tools through a constraints file, where it is used as the global PERIOD constraint. Multicycle paths are constrained to integer multiples of this value.
- HDL/Analysis
-
Block icon display:
- Specifies the type of information to be displayed on each block icon in the model after
compilation is complete. The various display options are described below.
-
Default:
- Displays the default block icon information on each block in the model. A block’s
default icon is derived from the
xbsIndex
library.
Figure 2. Default Block Icon - Displays the default block icon information on each block in the model. A block’s
default icon is derived from the
-
Normalized Sample Periods:
- Displays the normalized sample periods for all the input and output ports on each block. For example, if the Simulink System Period is set to 4 and the sample period propagated to a block port is 4 then the normalized period that is displayed for the block port is 1 and if the period propagated to the block port is 8 then the sample period displayed would be 2 for example, a larger number indicates a slower rate.
Figure 3. Normalized Sample Periods Icon
-
Sample frequencies (MHz):
- Displays sample frequencies for each block.
-
Pipeline stages:
- Displays the latency information from the input ports of each block. The displayed pipeline stage might not be accurate for certain high-level blocks such as the FFT, RS Encoder/Decoder, Viterbi Decoder, etc. In this case the displayed pipeline information can be used to determine whether a block has a combinational path from the input to the output. For example, the Up Sample block in the figure below shows that it has a combinational path from the input to the output port.
Figure 4. Sample Frequencies
-
HDL port names:
- Displays the HDL port name of each port on each block in the model.
-
Input data types:
- Displays the data type of each input port on each block in the model.
-
Output data types:
- Displays the data type of each output port on each block in the model.
-
Default:
- Specifies the type of information to be displayed on each block icon in the model after
compilation is complete. The various display options are described below.
- HLS
-
Target Subsystem:
- Select the subsystem name from the drop-down menu that needs to be targeted for HLS code generation.
- HLS/Settings
-
Target:
Target settings are shown in the following table.
Table 1. HLS Target Settings Setting Description IP Catalog Select IP Catalog to export the design to the Vivado IP Catalog. After C/C++ code generation, Vitis High-Level Synthesis (HLS) is invoked to synthesize the C code and create a project that can be exported as an IP to the Vivado IP Catalog. System Generator Select System Generator to export the design to HDL blockset. After C/C++ code generation, Vitis High-Level Synthesis (HLS) is invoked to synthesize the C code and create an RTL solution that can be used as a Vitis HLS block in a HDL model. HLS C++ Code Select HLS C++ code to compile the design model into C++ code. - Hardware Flow
- To generate the hardware image, specify the platform in the Target
pane and select the Create Testbench option in the AI
Engine/Settings pane.
- HW System Type: Choose between Baremetal or Linux hardware validation flow.
- Target: Specify the target for hardware validation flow.
- Generate
- Select a Subsystem containing blocks from the AI Engine, HDL, or HLS blocksets and specify the corresponding Code Directory. The Code Directory can be specified by entering the complete directory path or using the Browse button to provide a path.