Performing Standard Hardware Co-Simulation - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

If you are performing the standard (non-burst mode) hardware co-simulation, your Simulink model will contain a JTAG hardware co-simulation block. This block was created automatically when Model Composer finished compiling your design into an FPGA bitstream (see Compiling a Model for Hardware Co-Simulation). The block is stored in a Simulink library with this file name:


The hardware co-simulation block was moved into your Simulink model at the end of the compilation procedure. In the following procedure, you will have to wire up this block in your Simulink model to perform hardware co-simulation.

Note: If your board contains a Zynq® SoC device, you must install the Vitis™ unified software platform with the Vivado® Design Suite to perform hardware co-simulation.
Figure 1. Hardware Co-Simulation Block

To perform the standard hardware co-simulation:

  1. Connect the hardware co-simulation block to the Simulink blocks that supply its inputs and receive its outputs.

  2. Double-click the hardware co-simulation block to display the properties dialog box for the block.

  3. Fill out the block parameters in the properties dialog box.

    The properties are described in Block Parameters for the JTAG Hardware Co-Simulation Block.

  4. To set up the board for performing JTAG hardware co-simulation, you should connect a cable to the board’s JTAG port.

    For a description of the setup procedure for a JTAG hardware co-simulation, using a KC705 board as an example, see Setting Up a KC705 Board for JTAG Hardware Co-Simulation.

  5. In the Simulink model, simulate the model and the hardware by selecting Simulation > Run or clicking the Run simulation button.

    Running the simulation will simulate both the Model Composer design (or subsystem) in your Simulink model and the Xilinx device on your target board. You can then examine the results of the two simulations and compare the results to determine if the design implemented in hardware will operate as expected.