Performing Resource Analysis - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2022.1 English

Resource analysis can be performed whenever you generate any of the following compilation targets:

  • IP Catalog
  • Hardware Co-Simulation
  • Synthesized Checkpoint
  • HDL Netlist

To perform resource analysis in Model Composer:

  1. Double-click the System Generator token in the Simulink model.
  2. Select the following in the System Generator token dialog box:
    1. In the Compilation tab:
      • Specify the Part in which your design will be implemented.
        Note: If you select a Board instead of a Part, the Part field will be filled in with the name of the part on the selected Board.
      • Select one of the Compilation targets.

        Model Composer can perform resource analysis for any Compilation target you select.

      • Specify a Target Directory.
    2. In the Clocking tab:
      • Set the Perform Analysis field to Post Synthesis or Post Implementation based on the runtime vs. accuracy tradeoff.
      • Set the Analyzer type field to Resource.
    Figure 1. Resource Analyzer Generated by Your Tool
  3. In the System Generator token dialog box, click Generate.

    When you generate, the following occurs:

    1. Model Composer generates the required files for the selected compilation target. For resource analysis Model Composer invokes Vivado in the background for the design project.
    2. Depending on your selection for Perform analysis (Post Synthesis or Post Implementation), the design runs in Vivado through synthesis or through implementation.
    3. After the Vivado tools run is completed, resource utilization data is collected from the Vivado resource utilization database and saved in a specific file format under the target directory. At the end of the resource utilization data collection the Vivado project is closed and control is passed to the MATLAB/Model Composer process.
    4. Model Composer processes the resource utilization data and displays a Resource Analyzer table with resource utilization information (see below).
    Figure 2. Resource Analyzer

    In the resource analyzer table:

    • The header section of the dialog box indicates the Vivado design stage after which resource utilization data was collected from Vivado. This will be either Post Synthesis or Post Implementation.
    • The local toolbar contains the following commands to change the display of resource counts:
      • Hierarchical/Flat Display: Toggles the display between a hierarchical tree and a flattened list.
      • Collapse All: Collapses the design hierarchy to display only the top-level objects.
      • Expand All: Expands the design hierarchy at all levels to display resources used by each subsystem and each block in the design.
    • The number shown in each column heading indicates the total number of each type of resource available in the Xilinx device for which you are targeting your design. In the example below, the design is targeting a Kintex-7 FPGA.
      Figure 3. Resource Analysis Report for Kintex-7
    • The example displays a hierarchical listing of each subsystem and block in the design, with the count of the following resource types:
      block RAM and FIFO primitives.
      block RAMs (BRAMs) are counted in this way.
      Table 1. Number of BRAMs
      Primitive Type # BRAMs
      RAMB36E 1
      FIFO36E 1
      RAMB18E 0.5
      FIFO18E 0.5
      Variations of Primitives (for example, RAM36E1 and RAM36E2) are all counted in the same way.
      Total BRAMs = (Number of RAMB36E) + (Number of FIFO36E) + 0.5 (Number of RAMB18E + Number of FIFO18E)
      DSP48 primitives (DSP48E, DSP48E1, DSP48E2) and DSP58
      Registers and Flip-Flops. All primitive names that start with FD* (FDCE, FDPE, FDRE, FDSE, etc.) and LD* (LDCE, LDPE, etc.) are considered as Registers.
      All LUT types combined.
    • The display order can be sorted for any column’s values by clicking the column head.
    • You can cross probe from the table to the Simulink model by selecting a row in the table, which will highlight the corresponding HDL blocks in the Simulink model. See Cross Probing from the Resource Analysis Results to the Model.