HDL Netlist Compilation - 2022.1 English

Vitis Model Composer User Guide (UG1483)

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2022.1 English

The HDL Netlist compilation type produces HDL files that implement the design. More details regarding the HDL Netlist compilation flow can be found in the Compilation Results section.

As shown below, you may select HDL Netlist compilation by left-clicking the Compilation submenu control on the System Generator token dialog box, and selecting the HDL Netlist target.

Figure 1. HDL Netlist

The Board and Part fields allow you to specify the board or part for which you are targeting the HDL Netlist compilation. When you select a Board, the Part field automatically displays the name of the Xilinx® device on the selected Board, and this part name cannot be changed.

The HDL Netlist compilation can be performed for any of the boards or parts your Vivado tools support. In addition to accessing the Xilinx development boards installed as part of your Vivado installation, you can also specify Partner boards or custom boards (see Specifying Board Support in Model Composer HDL Blockset).

The files generated as part of an HDL Netlist compilation are placed in an hdl_netlist subdirectory under the directory you specified in the Target directory field. These files are described in the Compilation Results section.