Known Issues - 2022.1 English

Vitis Model Composer User Guide (UG1483)

Document ID
Release Date
2022.1 English

The following are some of the known issues:

  • The HWCosim Compilation Target is not supported for Multiple Clock Designs.
  • Only FIFO & Dual Port RAM blocks can be in the top-level of the design when using multiple clocks.
  • The behavior of blocks that aid in the crossing of Multiple clock domains is NOT cycle accurate.
  • Unconnected or terminated output ports cannot be viewed in the Waveform Viewer.