Specifying PLIOs in Model Composer Designs - 2022.1 English

Model Composer supports specifying the PLIO width using the AIE PLIO block and making external stream connections that cross the AI Engine to PL boundary.

Figure 1. AIE Signal Spec

The AIE PLIO block supports specifying the Platform IO (PLIO) width. Specifying the PLIO width at the boundary of the AI Engine subsystem can affect the throughput of data between the AI Engine domain and the programmable logic (PL) domain. You can also set the constraints for the PLIO block using its constraint manager.

Figure 2. Block Parameters: AIE PLIO

From the Parameters tab in the AIE Signal Spec block, you can select the available PLIO width options from the drop-down menu.

Consider following example where an AIE Signal Spec block is connected at the boundary of the AI Engine subsystem.

Figure 3. AIE PLIO Block Connected to AI Engine Subsystem

By default, the PLIO width is set to auto. Other available options are: 32, 64, and 128.

Figure 4. Block Parameters: AIE PLIO Width

After the PLIO width is specified as 64 and 128 for the two AIE PLIO blocks in the example, the GUI updates as follows.

Figure 5. AIE Signal Spec Blocks Updated

adf::input_plio PL_AIE_IN;
adf::output_plio AIE_PL_OUT;
 
   Subsystem() {
      PL_AIE_IN = adf::input_plio::create("PL_AIE_IN",
            adf::plio_64_bits,
            "./data/input/PL_AIE_IN.txt");
 
      AIE_PL_OUT = adf::output_plio::create("AIE_PL_OUT",
            adf::plio_128_bits,
            "AIE_PL_OUT.txt");
 
 adf::connect< > (PL_AIE_IN.out[0], mygraph.PL_AIE_IN);
 adf::connect< > (mygraph.AIE_PL_OUT, AIE_PL_OUT.in[0]);