This block is used to specify various properties on signals within, as well as at the boundary of an AI Engine subsystem.
Library
AI Engine/Tools
Description
The AIE Signal Spec block allows you to specify the Platform IO (PLIO) width and FIFO depth value within the AI Engine subsystem.
- Specifying the PLIO width at the boundary of the AI Engine subsystem will affect the throughput of data from the AI Engine domain to the programmable logic (PL) domain.
- Specifying the FIFO depth value can help avoid deadlock or stalling by creating more buffering in the paths.
Parameters
- Connection Tab
-
- FIFO Depth (32-bit words)
- Should be a positive integer value and the default value is '0'.
- Platform I/O Tab
-
- PLIO Width
- Only auto, 32, 64, and 128 are possible values. 'auto' is the default value.
- Specify PLIO frequency
- When set to ON, you can specify the Programmable logic frequency in MHz. The default value is 250 MHz. In general, choose a reasonable target frequency depending on the complexity of the algorithm implemented.